A Modified Domino Logic Circuit for Improved Noise Immunity and Delay Variability
نویسندگان
چکیده
This paper gives an approach for improvement in the reduction in delay variation in a domino logic circuits and it also gives improved noise immunity to the circuit. The improvement in delay observed here is better in the proposed circuit and the noise immunity is also enhanced by a good margin. The simulation process here is done by using Cadence Virtuoso 65nm process technology at 27 o C operating temperature and 0.8 V operating supply voltage (VDD) for the circuit.
منابع مشابه
Domino logic with variable threshold voltage keeper
A variable threshold voltage keeper circuit technique is proposed for simultaneous power reduction and speed enhancement of domino logic circuits. The threshold voltage of a keeper transistor is dynamically modified during circuit operation to reduce contention current without sacrificing noise immunity. The variable threshold voltage keeper circuit technique enhances circuit evaluation speed b...
متن کاملSpeed and Noise Immunity Enhanced Low Power Dynamic Circuits
Four different dynamic circuit techniques are proposed in this paper for lowering the active mode power consumption, increasing the speed, enhancing the noise immunity, and reducing the subthreshold leakage energy of domino logic circuits. A variable threshold voltage keeper circuit technique is proposed for simultaneous power reduction and speed enhancement of domino logic circuits. The thre...
متن کاملA Minimal-Cost Inherent-Feedback Approach for Low-Power MRF-Based Logic Gates
The Markov random field (MRF) theory has been accepted as a highly effective framework for designing noise-tolerant nanometer digital VLSI circuits. In MRF-based design, proper feedback lines are used to control noise and keep the circuits in their valid states. However, this methodology has encountered two major problems that have limited the application of highly noise immune MRF-based circui...
متن کاملFinFET domino logic with independent gate keepers
Scaling of single-gate MOSFET faces great challenges in the nanometer regime due to the severe shortchannel effects that cause an exponential increase in the sub-threshold and gate-oxide leakage currents. Double-gate FinFET technology mitigates these limitations by the excellent control over a thin silicon body by two electrically coupled gates. In this paper a variable threshold voltage keeper...
متن کاملDynamic Logic Styles with Improved Noise-immunity
Noise issues are becoming an important concern in digital systems due to the aggressive scaling trends in devices and interconnections. To address this problem a new noise-tolerant dynamic circuit technique suitable for dynamic logic styles is presented. Simulation results show that the proposed technique improves the ANTE by 3.4 and 2.8 over conventional dynamic True Single-Phase-Clock (TSPC) ...
متن کاملذخیره در منابع من
با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید
عنوان ژورنال:
دوره شماره
صفحات -
تاریخ انتشار 2014